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W89C880F f ast mpr 100base-tx/t4 multiport repeater controller publication release date: january 1997 - 1 - revision a1 general description the W89C880F , a 100base-t4/tx fast ethernet multiport repeater controller (fastmpr) , is designed for large fast ethernet networks. the W89C880F fastmpr complies fully with the ieee802.3u clause 27 repeater standard. the fastmpr offers a low-cost, high-performance solution to alleviate the hub- to - network traffic distance limitation that fast e thernet faces. two independent mii ports are provided: a normal mii port that can support up to 11 phy with the mii interface and an extension port that can easily extend the distance between the hub s to as far as 100 meters. the fastmpr implements a simple and limited bridge functions, such as address learning/filtering, runt packet filtering, and two types of packet forwarding function s: fragment free and store-and-forward. the extension port can be disabled by a hardware setting allowing it to act as a normal mii interface port . th e W89C880F offers a maximum of 12 ports. the device also supports one inter-fastmpr interface to con s truct a large hub with up to 6 fastmprs. the W89C880F implements enhanced network status report functions, such as network utilization report, individual port partition status report, individual port jabber status report, and collision report. the fastmpr also supports t4/tx and translation mode, simultaneously connecting to a t4 or tx physical layer controller with the mii interface . features functions conform to ieee802.3u clause 27 specifications supports up to 12 mii repeater ports t4/tx translation function asynchronous inter-fastmpr interface for up to 6 fastmpr hub application s a mii extension port with 100 meters hub-hub distance cascade capability limited bridge function: address learning/filtering, packet store/forwarding, fragment-free 32 kb 8, 64 kb 8, 128 kb 8 sram interface provided mii management function supported on-chip fifo elasticity for physical signal retiming port status direct report function on-chip network utilization report individual port, jabber/partition/reconnection state machine advanced cmos process for lower power dissipation single 5v power supply packaged in 160-pin pqfp
W89C880F f ast mpr - 2 - pin configuration txen3 121 vdd 122 link2 123 rxen2 124 crs2 125 txen2 126 link1 127 rxen1 128 crs1 129 txen1 130 dvdd 131 link0 132 rxen0 133 crs0 134 txen0 135 vss 136 tp0rpt 137 tp1rpt 138 tp2rpt 139 tp3rpt 140 dvss 141 tp4rpt 142 tp5rpt 143 tp6rpt 144 tp7rpt 145 vdd 146 tp8rpt 147 tp9rpt 148 tp10rpt 149 btprpt 150 xcolrpt 151 m3 152 m2 153 m1 154 m0 155 vss 156 mdc 157 mdio 158 / i c r s 1 / i b e n 2 v d d 3 i e r r 4 i d a t 3 5 i d a t 2 6 v s s 7 i d a t 1 8 i d a t 0 9 v d d 1 0 i d c l k 1 1 v s s 1 2 i j a m 1 3 / i c o l 1 4 d v d d 1 5 r t x c 1 6 d v s s 1 7 s a 0 1 8 s a 1 1 9 s a 2 2 0 s a 3 2 1 s a 4 2 2 s a 5 2 3 s a 6 2 4 s a 7 2 5 v d d 2 6 s a 8 2 7 s a 9 2 8 s a 1 0 2 9 s a 1 1 3 0 s a 1 2 3 1 s a 1 3 3 2 s a 1 4 3 3 s a 1 5 3 4 v s s 3 5 s a 1 6 3 6 / c s 0 3 7 / c s 1 3 8 sd2 43 sd3 44 vdd 45 sd4 46 sd5 47 sd6 48 sd7 49 vss 50 btxd0 51 btxd1 52 btxd2 53 btxd3 54 vdd 55 btxen 56 btxer 57 bcrs 58 brxdv 59 brxer 60 dvss 61 brxc 62 dvdd 63 brxd0 64 brxd1 65 brxd2 66 brxd3 67 blink 68 link10 69 rxen10 70 vss 71 crs10 72 txen10 73 link9 74 rxen9 75 crs9 76 txen9 77 vdd 78 link8 79 rxen8 80 l i n k 7 8 3 r x e n 7 8 4 c r s 7 8 5 t x e n 7 8 6 v s s 8 7 l i n k 6 8 8 r x e n 6 8 9 c r s 6 9 0 t x e n 6 9 1 v d d 9 2 t x d 0 9 3 t x d 1 9 4 v s s 9 5 t x d 2 9 6 t x d 3 9 7 v s s 9 8 t x e r 9 9 v d d 1 0 0 r x d v 1 0 1 r x e r 1 0 2 r x c 1 0 3 d v s s 1 0 4 r x d 0 1 0 5 r x d 1 1 0 6 d v d d 1 0 7 r x d 2 1 0 8 r x d 3 1 0 9 l i n k 5 1 1 0 c r s 5 1 1 2 t x e n 5 1 1 3 l i n k 4 1 1 4 r x e n 4 1 1 5 c r s 4 1 1 6 t x e n 4 1 1 7 l i n k 3 1 1 8 r x e n 3 1 1 9 c r s 3 1 2 0 / m s r d 3 9 / m s w r 4 0 test 159 t x e n 8 8 2 c r s 8 8 1 sd1 42 sd0 41 resetb 160 r x e n 5 1 1 1 figure 1
W89C880F f ast mpr publication release date: january 1997 - 3 - revision a1 pin description transceiver interface pins name no. i/o description crs<10:0> 72, 76, 81, 85, 90, 112, 116, 120, 125, 129, 134 i carrier sense input from phy. when the fastmpr receives a carrier sense signal from a specific port, it will echo rxen to that specific port. crs <10:0> refers to the carrier sense signal input of each port (tp10 - 0) . " 1 " means the carrier is present. rxen<10:0> 70, 75, 80, 84, 89, 111, 115, 119, 124, 128, 133 o/l receive enable output. rxen<10:0> refers to the receive enable output of ports tp10 - 0; 1 means receive is enabled. when crsn = 1 and the crs of other ports is deactiv ated, rxenn will be active and the fastmpr is ready to receive data. only one of rxen<10:0> can be active at a ny one time. txen<10:0> 73, 77, 82, 86, 91, 113, 117, 121, 126, 130, 135 o/l transmit enable output. txen<10:0> refers to the transmit enable output of ports tp10 - 0; "1" means transmit is enabled . when one of crs <10:0> = 1, txen will be active and the fastmpr is ready to transmit data to all other ports except the input port . link<10:0> 69, 74, 79, 83, 88, 110, 114, 118, 123, 127, 132 i phy link status input from phy. the fastmpr will propagate the input link status of phy, output the link status, and mix it with the received status information of each port in train to tp0 - 10rpt pins. rxd<3:0> 109, 108, 106, 105 i phy receive data. the fastmpr receives data from phy through these pins. data are synchronized with the rising edge of rxc. txd<3:0> 97, 96, 94, 93 o/h phy transmit data. fastmpr transmits data to phy through these pins. data are synchronized with the rising edge of rtxc. rxer 102 o phy receive error. "1" means an error has occurred in the data received from phy. txer 99 o/h fastmpr transmit error. "1" means that an rxer or fifo error ha s occurred. rxc 103 i receive clock. input from phy. this pin is used to synchronize the data received from phy. the fastmpr utilizes one of the rxen<10:0> signals to decide which rxc input from the receive enable port of phy should be cho sen . rtxc 16 i transmit clock. an input clock. this pin is used to synchronize fastmpr transmit data. rxdv 101 i receive data valid. input from phy. when high, phy has valid data present i n rxd<3:0>.
W89C880F f ast mpr - 4 - pin description, continued management interface pins name no. i/o description mdc 157 i management clock. input for fastmpr register read/write configuration. maximum clock rate is 2.5 mhz. this pin is used to synchronize with mdio. mdio 158 i/o/l management data. when the address of the mdio device matches the reset jumper setting of tp0 - 4rpt/ad<0:4 > on the fastmpr, the fastmpr will respond to the mdio read/write command. port status report/jumper setting pins tp0 - 4rpt/ ad<0:4> 137 - 140, 142 i/o/l tp0-4 port status output/fastmpr device address. after power- on reset, each of these pins can output the status train of one port, which sequentially reports four aspects of the fastmpr port status. the status train of each tpnrpt contains link/activity, partition, utilization, and jabber in sequence. the status train is latched by the signals m0 - 3. m0 is used to latch the link/activity status of all port s . m1 is used to latch the partition status of all port s . m2 is used to latch the network utilization at some instant in time. m3 is used to latch the jabber status. when these pins output the port status, they are active low. during power-on reset, these pins are used as the device address input pins of the fastmpr. if th e s e pin s are each connected with a pull-up resistor to the power supply, the input value of each pin is " 1 " . if no pull-up resistor is connected to the pin, the input value is " 0 " . when the mdio command address matches the device address, the fastmpr will respond to mdio read/write command s . tp5rpt/ disbg 143 i/o/l tp5 port status output /extension port enable. after power-on reset, this pin can sequentially output four aspects of tp5 port status : link/activity, partition, network utilization, and jabber. this pin outputs the port status, it is active low. during power-on reset, if no pull-up resistor is connected to this pin, the extension port is enabled. if a pull-up resistor is connected to this pin, the extension port is disabled. in this situation, the extension port acts as a normal mii interface and the fastmpr can support up to twelve ports. tp6rpt/ sramsel0 144 i/o/l tp6 port status output /sram size select. after power - on reset, this pin can sequentially output four aspects of tp6 port status : link/activity, partition, network utilization, and jabber. when the pin outputs the port status, it is active low. during power - on reset, if no pull-up resistor is connected to this pin, 64 k b data buffer is selected. if a pull-up resistor is connected to this pin, the buffer size is 128 k b .
W89C880F f ast mpr publication release date: january 1997 - 5 - revision a1 pin description, continued port status report/jumper setting pins name no. i/o description tp7rpt/ sramsel1 145 i/o/l tp7 port status output/sram interface select. after power - on reset, this pin can sequentially output four aspects of tp7 port status : link/activity, partition, network utilization , and jabber. when th is pin outputs the port status, it is active low. during power - on reset, if no pull-up resistor is connected to this pin, a 32 kb 8 2 or 64 kb 8 2 sram interface is selected. if a pull-up resistor is connected to this pin, then 64 kb 8 1 or 128 kb 8 1 buffer sram size is selected. tp8rpt/ fragsel0 147 i/o/l tp8 port status output /extension port fragment free window select 0. after power - on reset, this pin can sequentially output four aspects of tp8 port status : link/activity, partition, network utilization , and jabber. when this pin outputs the port status, it is active low. during power - on reset, regardless of whether a pull-up resistor is connected to this pin or not, the fastmpr can select a fragment - free window. the size of the fragment - free window is chosen by a combination of fragsel0 and fragsel1. tp9rpt/ fragsel1 148 i/o/l tp9 port status output / extension port fragment - free window select 1. after power - on reset, this pin can sequentially output four aspects of tp9 port status : link/activity, partition, network utilization, and jabber. when this pin outputs the port status, it is active low. during power - on reset, whether a pull-up resistor is connected to this pin or not, the fastmpr can select the fragment - free window. the size of the fragment - free window is chosen by fragsel0 and fragsel1 as shown below ( "0" means no pull-up resistor is connected, "1" means pull-up resistors are connected) . window value (bytes) disable 16 64 96 fragsel 0 1 0 1 0 fragsel 1 1 1 0 0 this is a limited tunable latency function for cut-through operation in filtering runt packets. tp10rpt 149 i/o/l tp10 port status output. after power - on reset, this pin can sequentially output four aspects of tp10 port status : link/activity, partition, network utilization , and jabber. btprpt 150 i/o/l extension port status output. after power - on reset, when the extension port is enabled, btprpt output s the link/activity status . if the extension port is disabled, btprpt sequentially output s the status train of link/activity, partition, netwok utilization , and jabber status. during the network utilization report period, this pin has no function. when this pin outputs the port status, it is active low.
W89C880F f ast mpr - 6 - pin description, continued port status report/jumper setting pins name no. i/o description xcolrpt 151 i/o/l any collision status output/carrier integrity monitor select. this is an active high pin. after power-on reset , this pin outputs the fastmpr port collision status (with the exception of the extension port). m0 155 o/l port status output select 0. after power-on reset, this output pin latches the link/activity status report from the tp0 - 10rpt and btprpt pins . m1 154 o/l port status output select 1. this output pin latches the partition status report from the tp0 - 10rpt and btprpt pins . m2 153 o /l port status output select 2. this output pin l atch es the n etwork utilization report from the tp0 - 9rpt pins. m3 152 o/l port status output select 3. this output pin latch es the j abber status report from the tp0 - 10rpt, btprpt pins. extension port interface pins bcrs 58 i extension port carrier input. this is the carrier sense signal coming from the fastmpr extension port. "1" means the extension port has carrier present. btxen 56 o/l extension port transmit enable output. "1" means the extension port is transmit enabled. brxd <3:0> 67 - 64 i extension port receive data. input data from phy connected to bridg e port . data are synchronous with the rising edge of brxc. btxd<3:0> 54 - 51 o/l extension port transmit data. output data from fastmpr . data are synchronous with the rising edge of rtxc. brxer 60 i extension port receive error. "1" means that an error has occurred in the data received by phy . btxer 57 o/l extension port transmit error. "1" means that an rxer or fifo error event has occur r ed. brxc 62 i extension port receive clock. input from phy . t his pin is used to synchronize the receiv ed data of phy connected to the extension port. brxdv 59 i extension port receive data valid. input from phy. "1" means phy has valid data present on brxd<3:0>. blink 68 i extension port link status input. input from phy. "1" means phy link is good. inter-f ast mpr interface pins idat<3:0> 5, 6, 8, 9 i/o/z inter-fastmpr interface data. these pins are used to cascade several fastmpr chips into one larger unit. the fastmprs use the inter-fastmpr interface to send/receive data to/from other fastmprs. the data are transmitted in nrz format. during idle state, idat<3:0> are in high - impedance state .
W89C880F f ast mpr publication release date: january 1997 - 7 - revision a1 pin description, continued inter-f ast mpr interface pins name no. i/o description idclk 11 i/o/z inter-fastmpr interface data clock. this is a bidirectional pin. if the fastmpr issues a carrier output to the integrator through its icrs pin , the integrator sends an acknowledge reply later through the iben pin to the fastmprs. once a n icrs has been issued and a valid iben has been received, the fastmpr send s idclk, ijam , and idat<3:0> to the inter-fastmpr interface integrator . the other fastmprs do not issue carrier outputs to the integrator , but instead receive idclk, ijam , and idat<3:0> from the integrator after receiving valid iben . if iben is not asserted, idclk is in high - impedance state . ierr 4 i/o/z inter-fastmpr interface data error. this pin indicates whether an error occur r ed during a interfastmpr interface transaction. when the fastmpr transmits data to the inter-fastmpr interface integrator, the assertion of ierr means a transmit error on the interface occu r red . when the fastmpr receives data from the inter-fastmpr interface integrator, the assertion of ierr means a receive error occur r ed on the interface. icrs 1 o/l inter-fastmpr interface carrier sense output. if asserted, the fastmpr will output a packet to the inter-fastmpr interface integrator . after the fastmpr that asserted icrs receives a valid iben from the integrator, the fastmpr will send data to idat<3:0>. iben 2 i inter-fastmpr interface enable. if asserted, the fastmpr that issued icrs earlier will output idat<3:0>, idclk, ijam , and ierr to the inter-fastmpr interface integrator. icol 14 i inter-fastmpr interface collision. "0" means a collision event has occur r ed. icol is asserted only when more than one fastmpr output s a carrier to the inter-fastmpr interface integrator at the same time. ijam 13 i/o/z inter-fastmpr interface jamming. when the fastmpr enter s the collision state, it asserts ijam and prop a gates ijam to the inter- fastmpr interface integrator. when another fastmpr receives ijam from an integrator, it means that a collision has occu r red on the other fastmpr. when ijam is asserted, the assertion of ierr means the fastmpr is in the one_port_left state, and the deassertion of ierr means the fastmpr is in the multi_fastmpr collision state.
W89C880F f ast mpr - 8 - pin description, continued sram interface pins name no. i/o description sa<16:0> 36, 34 - 27, 25 - 18 o/l sram address bus. the fastmpr supports different sram sizes for buffer use, including 32 kb 8, 64 kb 8 , and 128 kb 8. sa15, sa16 must be kept low when these two address pins are not used. sd<7:0> 49 - 46, 44 - 41 i/o/l sram data bus. cs0 37 o/l sram chip select 0. this pin is used to enable the bank 0 sram. cs1 38 o/l sram chip select 1. this pin is used to enable the bank 1 sram. msrd 39 o/l sram read command. mswr 40 o/l sram write command. miscellaneous reset 160 i fastmpr reset. this pin is active low. it needs a minimum 50 m s reset pulse width, when v dd is valid and stable. test 159 i test pin. set this pin to enter test mode. power/ground pins dv dd 15, 63, 107, 131 digital power supply. dv ss 17, 61, 104, 141 digital ground. v dd 92, 100 mii bus power supply. v ss 95, 98 mii bus ground. v dd 78, 122 mii port interface power supply. v ss 87, 136 mii port interface ground. v dd 146 led interface power supply. v ss 156 led interface ground. v dd 3, 10 inter-fastmpr interface power supply. v ss 7, 12 inter-fastmpr interface ground. v dd 55 extension port power supply. v ss 71 extension port ground. v dd 26, 45 sram interface power supply. v ss 35, 50 sram interface ground. note: "i" means input, "o" me an s output, "h" means 24 ma high drive/sink cell, "l" means 4 ma low drive/sink cell, and "z" means high- impedance.
W89C880F f ast mpr publication release date: january 1997 - 9 - revision a1 system diagram inter fastmpr interface mii mngrmnt bus sram interface mii interface port status report interface extension port 1 11 fastmpr figure 2 block diagram mux inter fastmpr logic fifo receive control logic fifo control repeat data handler main state machine carrier integrity monitor timers & counters port partition/jabber logic transmit control logic extension port management control logic transceiver transmit transceiver receive interface interface sram interface inter fastmpr interface figure 3 functional description basic mii port functions the media independent interface (mii) is an interface bus composed of 18 signal pins that is defined by the ieee802.3u specification. the mii offers a path for transferring data, status signals, and control signals between mac and phy. its functions are summarized below.
W89C880F f ast mpr - 10 - data transfer: the mii bus utilizes txd[0:3] and rxd[0:3] to transfer data. when an error occurs in phy, it will assert the rxer pin on the hub and then the hub asserts txer on every other port. media status: if phy detects a collision or carrier, it will notify the fastmpr that a collision has occurred, that the link status is good, and so forth. management function: the fastmpr has four hardware-dependent registers, which are controlled by both the mii interface and pin settings. the details are described in the mii management section. this interface is used to provide media independence for various types of wiring, such as unshielded twisted pair, shielded twisted pair, fiber optic cable, and potentially other media. a media access device can be used with this interface to form a lan adapter or a hub port with any of these media. the fastmpr provides two mii interfaces. one interface is for general purpose use; it supports the mii management function and can drive up to 11 physical layers. the other interface provides fast ethernet network extension functions. the extension port implementation allows a 100 mbps fast ethernet network to be easily segmented with a network distance limitation of 100 meters (similar to 10 mbps ethernet). a fastmpr application is shown in the following diagram. general application arch i tecture fastmpr icrs iben icol idclk ijam ierr idat<3:0> fastmpr icrs iben icol idclk ijam ierr idat<3:0> mii mii phy & xcvr1 phy & xcvr2 phy & xcvr11 .... extension port sram 100 meters any other hub inter fastmpr interface integrator figure 4 the following s ection gives a detailed description of each fastmpr function block : mii port switch the fastmpr connects to the physical layer controller (phy) through the input pins rxdv, rxer, rxc, and rxd<3:0> and the output pins txer and txd<3:0>. the direction of the data or signal transfer is assigned by the fastmpr by asserting txen or rxen. when it asserts txen, the fastmpr is ready to regenerate and transfer packets to the connected port. the phy device will then fetch the packet and put it on the media through the pmd transceiver. when phy sends out a crs, the fastmpr asserts rxen to this phy, before repeating this packet to all other tp ports.
W89C880F f ast mpr publication release date: january 1997 - 11 - revision a1 mii data error handling if a receive error occurs while the phy controller is receiving data, the controller will issue a receive error signal rxer to the fastmpr. the fastmpr will then repeat the data stream to all other ports after a short delay. the fastmpr will also assert txer at the location rxer to indicate that there is a receive error at this location. frame rxer t frame txer t figure 5 in the figure shown above, the upper timing diagram represents the receiving port, and the lower diagram is a repeated frame with some hub latency. these two timing diagrams are similar and keep the same t latency between the sfd (start of frame delimiter) and error signal (rxer, txer). mii port collision and jam generation the fastmpr also monitors the input signals crs0 - 10. if more than one carrier appears at the same time, the fastmpr will issue a jamming pattern to all its output ports, while reporting the collision status to the direct report pin xcolrpt. after the collision has been detected, the fastmpr will immediately append the jamming pattern to all the connected ports until all network nodes stop transmitting data frames, only one node is active, or a power-on reset occurs. figure 6 shows how the fastmpr enters and leaves the collision state. auto partition/reconnection the fastmpr implements an auto partition/reconnection function to protect the network from failure caused by consecutive collisions from a specific port on the fastmpr. each port on the fastmpr implements an independent auto partition/reconnection state function. the port will automatically partition itself when 64 or more consecutive collisions occur on the same port (the ieee802.3 standard is greater than 60). a port will automatically recover to its active state after either successfully transmitting more than 512 bits of data continuously without collision on the same port (ieee802.3 defines this figure to be between 450 and 560 bits) or after a power-on reset. when a port is partitioned, the fastmpr does not allow any input messages to pass from the port, but can accept output messages from the hub internal to the partitioned port.
W89C880F f ast mpr - 12 - collision and jam diagram start idle one port is active command (allxn) = copy command (n) = quiet command (all) = collision jam active active node > 1 all is quite active node > 1 all_data_sent active node = 1 and active node = 1 active node = 1 reset or power on figure 6 fastmpr partition diagram connect partition state consecutive collision number > = 64 more than 512 bits are transmitted without collision or power on reset figure 7 jabber protection the jabber protection function prevents reception of illegally long packets, which would degrade network performance. when a fastmpr port receives a packet longer than 65536 bits, the jabber function cuts the data frame, and the receive/transmit path of the port is disabled. then no data frame, regardless of whether it is from an input or output end, can pass through the port unless the carrier on the port is no longer detected or the fastmpr is reset (by being switched off and then on again). the jabber timer specification of fast ethernet is 40000 - 75000 bit times.
W89C880F f ast mpr publication release date: january 1997 - 13 - revision a1 carrier integrity monitor the carrier integrity monitor function can be activated only in the 100basetx physical layer controller (phy) and is neglected in t4 phy. the fastmpr monitors this carrier activity and utilizes four types of timers to judge whether a carrier is distinguishable. the four timers are the false carrier timer (480 bits time), idle timer (33792 bits), ipg timer (80 bits), and valid carrier timer (480 bits). the standard ieee802.3u specifications for these items are the following: false carrier timer: 450 - 500 bit-time idle timer: 33000 25% bit-time ipg timer: 64 - 86 bit-time valid carrier timer: 450 - 500 bit-time the carrier integrity monitor state machine will force a port to enter the isolation state to prevent a malfunctioning port from disturbing the network segment. if the j and k patterns defined in 4b/5b coding table occur, so that the carrier in the start of preamble is combined with so much noise that it cannot be distinguished by the phy controller, then phy will put a false carrier packet on the mii bus. if two consecutive false carrier events occur on a fastmpr port or a false carrier event occurs and lasts for a time that exceeds the default value of the false timer register, the port will be forced into isolation mode and its transmit/receive path will be inhibited. a port in the isolation state will return to operating state when the medium is idle for more than the summation of the set value of the idle timer and ipg timer or when both the carrier is absent and the valid carrier timer has timed out. pcs code group <4:0> code name mii (txd/rxd) <3:0> remark 11110 0 0000 data 0 01001 1 0001 data 1 10100 2 0010 data 2 10101 3 0011 data 3 01010 4 0100 data 4 01011 5 0101 data 5 01110 6 0110 data 6 01111 7 0111 data 7 10010 8 1000 data 8 10011 9 1001 data 9 10110 a 1010 data a 10111 b 1011 data b 11010 c 1100 data c 11011 d 1101 data d 11100 e 1110 data e 11101 f 1111
W89C880F f ast mpr - 14 - continued 11111 i undefined idle; used as interstream fill code 11000 j 0101 start-of-stream delimiter 10001 k 0101 start-of-sream delimiter 01101 t undefined end-of-sream delimiter 00111 r undefined end-of-sream delimiter 4b/5b code group mii management the fastmpr provides a set of configuration registers, accessible through the mdc and mdio pins on the mii serial management bus. the fastmpr can thus be managed through the mdc and mdio pins. for the fastmpr to be configured by programming these registers or setting hardware jumpers, an external serial command generator is needed to generate an mii management frame format command (shown in the following table) to drive mdc with a minimum 400 ns clock period so that the data train is latched on the mdio. the typical read and write timing of the serial interface is shown in the diagram below (figure 8 and figure 9). mii management protocol pre st op phyad regad ta data idle read 1... 1 01 10 aaaaa rrrrr z0 16 bits z write 1... 1 01 01 aaaaa rrrrr 10 16 bits z management frame format table note: pre: preample; st: start of frame; op: operation code; phyad: phy address; regad: register address. ta: turnaround. typical mdio/mdc read cycle high impedance(z) z .... idle start read phyad regad ta data idle 1 0 z 0 mdc mdio .... preamble 0 1 figure 8 typical mdio/mdc write cycle z .... idle start write phyad regad ta data idle 1 0 mdc mdio .... preamble 0 1 0 1 figure 9
W89C880F f ast mpr publication release date: january 1997 - 15 - revision a1 the fastmpr implements a total of 3 mii registers for users . e ach function is described as follows: normal command registers register bit name r/w description 0 0 - 11 port_disable r/w tp0 - 10 and extension port are enabled when these bits are reset. tp0 - 10 and extension port are disabled when these bit s are set. 0 12 sram_select0 r/w 64k byte sram size is selected when this bit is reset. 128k byte sram size is selected when this bit is set. 0 13 sram_select1 r/w 32 kb 8 2 or 64 kb 8 2 sram interface i s selected when this bit is reset. 64 kb 8 1 or 128 kb 8 1 sram interface i s selected when this bit is set. 0 14 bridge_disable r/w extension port function is enabled when this bit is reset extension port function is disabled when this bit is set. 0 15 reserved. 1 0 - 11 partition_status r bit 0 - 11 show the partition status of tp0 - 10 ports and extension port. tp0 - 10 and extension port are connected when these bits are reset. tp0 - 10 and extension port are partitioned when these bits are set. 1 12 - 15 reserved. 2 0 - 11 jabber_status r bit 0 - 11 show the jabber status of tp0 - 10 ports and extension port. tp0 - 10 and extension port are in jabber when these bits are set. 2 12 - 15 reserved. notes: 1. the bit 11 of registers 1, 2 reports the partition, jabber . these status function s are reported only when the extension port is disabled. 2. "r" means read only, "w" means write only, "r/w" means read/write. port status direct report the port status direct report is the easiest way to obtain information on the network status. the fastmpr xcolrpt output pin provides a collision status report. four pins (m0 - 3) are used to select the type of status report and latching. twelve pins, tp0 - 10rpt and btprpt, report the port status. each pin can sequentially report four aspects of the port status: link/activity, partition, utilization, and jabber. the xcolrpt report is asserted whenever a collision occurs in the fastmpr. pins m0 - 3 determine the aspect of the network status reported on the twelve port status pins. the fastmpr reports the network status to a set of leds, which are driven through an external driver ic. the timing chart for the status display pins m0 - 3 versus the port status data train is shown in the figure below.
W89C880F f ast mpr - 16 - link/activity partition network utilization jabber m0 m1 m2 m3 10 ms figure 10 as the figure above shows, the led report can be easily implemented. each of the port status report pins outputs the port status and is sequentially latched by an external ic at the rising edge of the m0 - 3 pulse. in the tp link/activity report section, a low output from tp0 - 10rpt and btprpt indicates that the tp ports and the extension port are in link good state. a high output indicates that the tp ports and extension port are not in link good state, and the led is lit. if a data frame is passing through the port, a 10 hz signal with a half duty cycle is output to flash the leds through a driving circuit to show that the tp port is receiving packets. note that when the tp ports have incoming packets, the link/activity signal is still reported even if the ports are partitioned or disabled. in the partition status report section, a high output from tp0 - 10rpt means the traffic on each fastmpr port connected to a network segment or a node is flowing smoothly. a low output on tp0 - 10rpt means the tp ports are in the partition state, and btprpt is undefined during this time. in this mode, the led will be kept on when a port is partitioned. in the network utilization report status section, tp0 - 9rpt will output the network utilization status, and the tp10rptand btprpt pins are undefined. the winbond fastmpr uses a proprietary technique to smoothly control the network utilization display, which is usually handled by the cpu. the fastmpr counts every bit, including preamble, runt packets, and so on, running over the media, so that it can display practical information on network utilization. it samples this counted value every 40 ms to determine which leds should be lit, so that the led will be lit on or off in a smooth and ordering fashion. the relationship between utilization and the leds is described in the table below. in the jabber status report section, a low output from the tpnrpt (n = 0, 1, ..., 10) pins indicates the tp ports are in the jabber state. a high output indicates the tp ports are not in the jabber state. at this time, btprpt has no function. when the extension port is disabled, the output behavior of btprpt will be the same as that of tp0 - 10rpt. the pin/utilization report combinations are shown in the following table: pin/utilization report 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% tp0rpt 1 0 0 0 0 0 0 0 0 0 0 tp1rpt 1 1 0 0 0 0 0 0 0 0 0 tp2rpt 1 1 1 0 0 0 0 0 0 0 0 tp3rpt 1 1 1 1 0 0 0 0 0 0 0 tp4rpt 1 1 1 1 1 0 0 0 0 0 0 tp5rpt 1 1 1 1 1 1 0 0 0 0 0
W89C880F f ast mpr publication release date: january 1997 - 17 - revision a1 continued tp6rpt 1 1 1 1 1 1 1 0 0 0 0 tp7rpt 1 1 1 1 1 1 1 1 0 0 0 tp8rpt 1 1 1 1 1 1 1 1 1 0 0 tp9rpt 1 1 1 1 1 1 1 1 1 1 0 network utilization vs led status calculation window |------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------|------| utilization result 0 100 100 100 100 100 80 80 80 80 90 60 0 0 0 0 0 0 utilization report 0 10 20 30 40 50 60 70 80 80 90 80 70 60 50 40 30 20 (smoothly rise) (halt) (smoothly drop) (100 ms per segment) figure 11 note: "halt" means that the utilization report cannot be larger than the real network utilization result. inter-fastmpr interface the fastmpr implements the inter-fastmpr interface for large scale repeater applications. up to 6 fastmprs can be put in to one repeater unit using the inter-fastmpr interface integrator. an extra integrator is needed to handle hub cascading. the inter-fastmpr interface is composed of idat<3:0>, icrs , iben , icol , ijam, ierr, and idclk. the inter-fastmpr interface adopts asynchronous operation, a frequency-phase-independent technique. regardless of whether a single or multiple oscillator frequency source is used, the fastmpr cascades or stacks easily and each fastmpr connected to the inter-fastmpr interface integrator works well. idclk is used to synchronize the data idat<3:0> transferred between fastmprs. ierr is used to indicate that the repeated data contain errors. ierr also propagates this error message to other fastmprs. icrs is used to output the fastmpr carrier to the integrator. when the fastmpr receives iben after icrs is asserted, the fastmpr that asserted icrs will put the transmitted data into idat<3:0> and propagates it to the inter-fastmpr interface integrator. if the fastmpr does not issue an icrs assertion but receives iben from the integrator, the fastmpr is ready to receive data from the integrator. if the integrator receives more than one icrs asserted from different fastmprs, it will pull icol low so that all the fastmprs connected to the integrator can detect that a collision event has occurred. at this time, the fastmpr that asserted icrs will append ijam to the inter-fastmpr interface integrator. extension port functions the fast ethernet class 2 architecture has a limit of 205 meters. this means that the maximum length allowed between two 100basetx repeaters is only 5 meters. the W89C880F implements an extension port to overcome this limitation while maintaining a setup similar to 10base-t ethernet. the
W89C880F f ast mpr - 18 - extension port functions extend the distance between two 100basetx repeaters and partition the traffic and collisions among fast ethernet hubs. the extension port function is optional; the default setting is enabled. the extension port can also be disabled so that it functions as a normal port. to disable the extension port, place a 10k ohm pull-high resistor on the pin tp5rpt/disbg, and power it on. when the extension port is disabled, the extension port mii interface acts as a normal mii port. the extension port function is described below. frame buffer interface the extension port provides three types of sram interfaces, 32k 8, 64k 8, and 128k 8 sram, and two optional sram buffer sizes, 64k bytes and 128k bytes. the default sram buffer size is 64 kb, and the default sram interface is 32 kb 8. the sram buffer size and sram interface are programmable and are controlled by tp6rpt/sramsel0 and tp7rpt/sramsel1, respectively. if a 10k ohm pull-high resistor is connected to the pin tp6rpt/sramsel0, the sram buffer size will be 128 kb; otherwise, it is 64 kb. if a 10k ohm pull-high resistor is connected to the pin tp7rpt/sramsel1, the sram buffer interface will support one sram chip; otherwise, it will support two chips. the combinations permitted are listed in the table below. tp6rpt tp6rpt +10k w tp7rpt tp7rpt +10k w buffer size 64 kb 128 kb buffer interface 2s sram 1 sram sram configuration table store and forward if enabled, the extension port will store packets in the buffer when the network segment on the other side of the extension port is busy. once a complete packet is received and the opposing network segment is quiet, the packet will be forwarded. while the packet is being forwarded, any collision will abort the operation and force the fastmpr to enter a backoff period. when the backoff time has elapsed, the extension port reattempts to transmit the packet until the operation is successful or the backoff time is truncated. if the buffer is empty and the opposing network is quiet, the packet transmitted will pass directly through the port and will not be stored in the sram buffer. not all packets can be forwarded; forwarding depends on the contents of the address filtering table. if the destination node, which has registered its address to the extension port, is located on the same side as the source node, the packet will not be stored and forwarded. fragment-free window the extension port directly forwards a packet if the length of the received packet exceeds the value set in the fragment-free window and if the opposed network segment is quiet. otherwise, the packet will be stored in the buffer. the fragment-free function discards bad packets caused by a crc error, alignment error, or receive error, long packets (longer than 1518 bytes), and runt packets caused by collision events. learning and filtering the extension port provides two internal hash tables with 128 address entries each for learning and filtering. one table is used for the source address, and the other for the destination address. after power on, the extension port resets the two address tables and starts to fill the address table by extracting the source address and the destination address from the received packet through a mapping function. about 40 minutes after power on, the fastmpr begins the address filter function.
W89C880F f ast mpr publication release date: january 1997 - 19 - revision a1 at this time, a packet with a destination address that matches an address in the destination address table will pass through the extension port to the opposing network segment. otherwise, the packet will not be stored and forwarded. absolute maximum ratings parameter sym. minimum maximum unit operating temperature t a 0 70 c storage temperature t s -55 150 c supply voltage v dd -0.5 7.0 v input voltage v in v ss -0.5 v dd +0.5 v output voltage v out v ss -0.5 v dd +0.5 v lead temperature (soldering 10 seconds maximum) t l -55 250 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. power supply (v dd = 4.75 to 5.25v, v ss = 0v, t a = 0 c to 70 c) parameter symbol typical maximum unit power supply current (idle) i ddi - 150 ma power supply current i ddl - 250 ma dc characteristics (v dd = 4.75v to 5.25v, v ss = 0v, t a = 0 c to 70 c) digital parameter symbol minimum maximum unit low input voltage v il v ss -0.5 0.8 v high input voltage v ih 3.85 v dd +0.5 v low output voltage (v dd = 4.5v) v ol 0.4 v high output voltage (v dd = 4.5v) v oh 2.4 v input leakage current (note 1) i il1 10 m a input current (note 2) i il2 500 m a output leakage current (v dd = 5.5v) i ol 10 m a notes: 1. all of the input pins except those stated in note 2. 2: test, iben , icol these pins had been pull low or pull high. mii interface parameter symbol minimum maximum unit
W89C880F f ast mpr - 20 - low input voltage v il 0.8 v high input voltage v ih 2 v low output voltage (at i ol = 24 ma) v ol 0.4 v high output voltage (at i oh = -24 ma) v oh 2.4 v input high current (v i = 5.25v) (note) i ih1 200 m a mdc input high current (v i = 5.25v) i ih2 20 m a mdio input high current (v i = 5.25v) i ih3 3000 m a input low current (v i = 0v) (note) i il1 -20 m a mdc input low current (v i = 0v) i il2 -20 m a mdio input low current (v i = 0v) i il3 -180 m a output leakage current (v dd = 5.5v) i ol 10 m a note: all of the mii input pins except mdc, mdio pins input low/high current. sram read sd0-7 msrd cs0, cs1 sa0-16 t1 t2 t3 t4 t5 t6 t7 figure 12 symbol description min typ. max unit t1 read cycle time 30 ns t2 address valid to chip select valid delay time 1 ns t3 cs0 , cs1 command width 30 ns t4 address valid to read command valid delay time 6 ns t5 msrd command width 15 ns t6 sd0-7 setup time 3 ns t7 sd0-7 hold time 3 ns sram write
W89C880F f ast mpr publication release date: january 1997 - 21 - revision a1 sd0-7 mswr cs0, cs1 sa0-16 t1 t2 t3 t4 t5 t6 t7 figure 13 symbol description min typ. max unit t1 write cycle time 30 ns t2 address valid to chip select valid delay time 1 ns t3 cs0 , cs1 command width 30 ns t4 address valid to write command valid delay time 6 ns t5 mswr command width 15 ns t6 mswr active to sd0-7 valid delay time 2 ns t7 mswr inactive to sd0-7 inactive delay time 3 ns ac characteristics (v dd = 4.75v to 5.25v, v ss = 0v, t a = 0 c to 70 c) mii interface input timing t1 t2 rxc rxd, rxdv rxen, rxer t3 t4 t5 t6 figure 14 symbol description min typ. max unit t1 rxc clock cycle 39.996 40 40.004 ns t2 rxc clock high time 14 20 26 ns t3 rxc rise time 4 ns t4 rxc fall time 4 ns t5 mii input setup time 10 ns t6 mii input hold time 10 ns
W89C880F f ast mpr - 22 - mii interface output timing t1 rtxc txd, txen, txer t2 t3 t4 t5 figure 15 symbol description min. typ. max. unit t1 rtxc clock cycle 39.996 40 40.004 ns t2 rtxc clock high time 14 20 26 ns t3 rtxc rise time 4 ns t4 rtxc fall time 4 ns t5 rtxc to mii signal output delay time 0 25 ns mii management output timing t1 t2 mdc mdio figure 16 symbol description min. typ. max. unit t1 mii management output setup time 10 ns t2 mii management output hold time 10 ns mii management input timing t1 mdc mdio figure 17 symbol description min. typ. max. unit t1 mii management input delay time 0 300 ns
W89C880F f ast mpr publication release date: january 1997 - 23 - revision a1 mii port receive timing crsm rxc rxenm txenn t1 t2 figure 18 symbol description min. typ. max. unit t1 crs input to rxen output delay time 8 10 bt t2 crs in to txen out propagation delay 12 bt mii port collision propagation delay timing crsm rtxc t1 txenn t2 crsn figure 19 symbol description min. typ. max. unit t1 second crs input to txen (jam) output delay time 12 bt t2 second crs end to txen (jam) end delay time 12 bt mii port transmit timing rtxc txen t1 rxen figure 20 symbol description min. typ. max. unit t1 rxen active to txen output delay 40 ns
W89C880F f ast mpr - 24 - inter-fastmpr interface input timing idclk icrs iben idat ijam 1 2 high_z high_z ierr icol figure 21 no. description min. typ. max. unit 1 idat/ijam/ierr to idclk setup time 5 35 ns 2 idat/ijam/ierr to idclk hold time 5 35 ns inter-fastmpr interface output timing idclk 2 1 icrs iben 3 4 icol idat ijam high_z high_z ierr figure 22 no. description min. typ. max. unit 1 icrs asserted to iben asserted 20 ns 2 icrs deasserted to iben deasserted 20 ns 3 transmit -out idat/ijam/ierr setup time to transmit- out idclk rising 13 ns 4 transmit -out idat/ijam/ierr hold time from transmit - out idclk rising 13 ns
W89C880F f ast mpr publication release date: january 1997 - 25 - revision a1 inter_fastmpr interface propagation delay t1 t2 crs icrs txen iben figure 23 symbol description min. typ. max. unit t1 mii to inter-fastmpr interface propagation delay 16 bt t2 inter-fastmpr interface to mii propagation delay 12 bt digital output switching test load 50pf figure 24 mii output switching test load 68 ohm figure 25
W89C880F f ast mpr - 26 - package dimensions 160-pin pqfp h d d e b e h e y a a seating plane l l 1 see detail f detail f c 1 a 2 1 40 120 81 41 80 160 121 1. dimension d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeters 4. general appearance spec. should be based on final visual inspection spec. 0.10 0 12 0 0.004 1.60 1.00 31.50 0.80 31.20 0.60 30.90 0.063 0.039 1.240 0.031 1.228 0.023 1.216 0.65 28.13 0.25 0.40 3.36 3.68 28.00 3.23 27.87 0.10 0.25 3.10 0.10 1.107 0.010 0.016 0.132 0.145 1.102 0.127 0.026 1.097 0.004 0.010 0.122 0.004 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.012 0.006 0.15 0.30 12 1.097 1.102 1.107 27.87 28.00 28.13 1.216 1.228 1.240 30.90 31.20 31.50 0.020 0.032 0.055 0.071 0.50 0.80 1.40 1.80 q figure 26 headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792646 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-7197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-7190505 fax: 886-2-7197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2730 orchard parkway, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-9436668 note: all data and specifications are subject to change without notice.

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